/* 
 ********************************************************************
 * Project:     GNU-Port TCP/IP-Stack
 * File:    	peripherals_lpc23xx.h
 *
 * System:   	ARM7TDMI-S 32 Bit
 * Compiler:  	GCC 4.0.3
 *
 * Date:      	2006-08-31
 * Author:    	Wenz
 *
 * Rights:    	Hitex Development Tools GmbH
 *            	Greschbachstr. 12
 *            	D-76229 Karlsruhe
 ********************************************************************
 * Description:
 *	
 * definitions and Bit masks for the LPC23xx hardware
 * registers 
 ********************************************************************
 * History:
 *
 *  Revision 1.0    2006/09/27      We
 *     Initial revision 
 ********************************************************************
 * This software is provided by the author 'AS IS' without any 
 * warranties. Hitex Development Tools GmbH shall not be held 
 * liable for any direct, indirect or consequential damages with
 * respect to any claims arising from the content of such software.
 ********************************************************************/


#ifndef _PERIPHERALS_LPC23XX_H_
#define _PERIPHERALS_LPC23XX_H_


#include "defines.h"


/*
 *********************************************************************
 * PIN Connect Block 
 *********************************************************************
 */

#define PINSEL0        (*(REG32 0xE002C000))
#define PINSEL1        (*(REG32 0xE002C004))
#define PINSEL2        (*(REG32 0xE002C008))
#define PINSEL3        (*(REG32 0xE002C00C))
#define PINSEL4        (*(REG32 0xE002C010))
#define PINSEL5        (*(REG32 0xE002C014))
#define PINSEL6        (*(REG32 0xE002C018))
#define PINSEL7        (*(REG32 0xE002C01C))
#define PINSEL8        (*(REG32 0xE002C020))
#define PINSEL9        (*(REG32 0xE002C024))
#define PINSEL10       (*(REG32 0xE002C028))

// each PIN could have up to 4 software selectable functions
#define PINFUNC1		0x00
#define PINFUNC2		0x01
#define PINFUNC3		0x02
#define PINFUNC4		0x03


/*
 *********************************************************************
 * Power Control 
 *********************************************************************
 */
 
#define PCON           	(*(REG32 0xE01FC0C0))	// power control
#define PCONP          	(*(REG32 0xE01FC0C4))	// interrupt wake
#define INTWAKE			(*(REG32 0xE01FC1444	// power control for peripherals

// peripheral Bits for peripherals power control 
#define PCON_TIM0		0x00000001
#define PCON_TIM1		0x00000002
#define PCON_UART0		0x00000004
#define PCON_UART1		0x00000008
#define PCON_ENET		0x40000000

/*!
 *********************************************************************
 * Vectored Interrupt Controller (VIC) 
 *********************************************************************
 */

#define		VIC_Base	0xFFFFF000;


#define VICIRQStatus   		(*(REG32 0xFFFFF000))
#define VICFIQStatus   		(*(REG32 0xFFFFF004))
#define VICRawIntr     		(*(REG32 0xFFFFF008))
#define VICIntSelect   		(*(REG32 0xFFFFF00C))
#define VICIntEnable   		(*(REG32 0xFFFFF010))
#define VICIntEnClr    		(*(REG32 0xFFFFF014))
#define VICSoftInt     		(*(REG32 0xFFFFF018))
#define VICSoftIntClr  		(*(REG32 0xFFFFF01C))
#define VICProtection  		(*(REG32 0xFFFFF020))
#define VICSWPriorityMask  	(*(REG32 0xFFFFF024))

#define VICVectAddr    (*(REG32  0xFFFFFF00))

#define VICVectAddr0   (*(REG32  0xFFFFF100))
#define VICVectAddr1   (*(REG32  0xFFFFF104))
#define VICVectAddr2   (*(REG32  0xFFFFF108))
#define VICVectAddr3   (*(REG32  0xFFFFF10C))
#define VICVectAddr4   (*(REG32  0xFFFFF110))
#define VICVectAddr5   (*(REG32  0xFFFFF114))
#define VICVectAddr6   (*(REG32  0xFFFFF118))
#define VICVectAddr7   (*(REG32  0xFFFFF11C))
#define VICVectAddr8   (*(REG32  0xFFFFF120))
#define VICVectAddr9   (*(REG32  0xFFFFF124))
#define VICVectAddr10  (*(REG32  0xFFFFF128))
#define VICVectAddr11  (*(REG32  0xFFFFF12C))
#define VICVectAddr12  (*(REG32  0xFFFFF130))
#define VICVectAddr13  (*(REG32  0xFFFFF134))
#define VICVectAddr14  (*(REG32  0xFFFFF138))
#define VICVectAddr15  (*(REG32  0xFFFFF13C))
#define VICVectAddr16  (*(REG32  0xFFFFF140))
#define VICVectAddr17  (*(REG32  0xFFFFF144))
#define VICVectAddr18  (*(REG32  0xFFFFF148))
#define VICVectAddr19  (*(REG32  0xFFFFF14C))
#define VICVectAddr20  (*(REG32  0xFFFFF150))
#define VICVectAddr21  (*(REG32  0xFFFFF154))
#define VICVectAddr22  (*(REG32  0xFFFFF158))
#define VICVectAddr23  (*(REG32  0xFFFFF15C))
#define VICVectAddr24  (*(REG32  0xFFFFF160))
#define VICVectAddr25  (*(REG32  0xFFFFF164))
#define VICVectAddr26  (*(REG32  0xFFFFF168))
#define VICVectAddr27  (*(REG32  0xFFFFF16C))
#define VICVectAddr28  (*(REG32  0xFFFFF170))
#define VICVectAddr29  (*(REG32  0xFFFFF174))
#define VICVectAddr30  (*(REG32  0xFFFFF178))
#define VICVectAddr31  (*(REG32  0xFFFFF17C))

#define VICVectPriority0   (*(REG32 0xFFFFF200) )
#define VICVectPriority1   (*(REG32 0xFFFFF204))
#define VICVectPriority2   (*(REG32 0xFFFFF208))
#define VICVectPriority3   (*(REG32 0xFFFFF20C))
#define VICVectPriority4   (*(REG32 0xFFFFF210))
#define VICVectPriority5   (*(REG32 0xFFFFF214))
#define VICVectPriority6   (*(REG32 0xFFFFF218))
#define VICVectPriority7   (*(REG32 0xFFFFF21C))
#define VICVectPriority8   (*(REG32 0xFFFFF220))
#define VICVectPriority9   (*(REG32 0xFFFFF224))
#define VICVectPriority10  (*(REG32 0xFFFFF228))
#define VICVectPriority11  (*(REG32 0xFFFFF22C))
#define VICVectPriority12  (*(REG32 0xFFFFF230))
#define VICVectPriority13  (*(REG32 0xFFFFF234))
#define VICVectPriority14  (*(REG32 0xFFFFF238))
#define VICVectPriority15  (*(REG32 0xFFFFF23C))
#define VICVectPriority16  (*(REG32 0xFFFFF240))
#define VICVectPriority17  (*(REG32 0xFFFFF244))
#define VICVectPriority18  (*(REG32 0xFFFFF248))
#define VICVectPriority19  (*(REG32 0xFFFFF24C))
#define VICVectPriority20  (*(REG32 0xFFFFF250))
#define VICVectPriority21  (*(REG32 0xFFFFF254))
#define VICVectPriority22  (*(REG32 0xFFFFF258))
#define VICVectPriority23  (*(REG32 0xFFFFF25C))
#define VICVectPriority24  (*(REG32 0xFFFFF260))
#define VICVectPriority25  (*(REG32 0xFFFFF264))
#define VICVectPriority26  (*(REG32 0xFFFFF268))
#define VICVectPriority27  (*(REG32 0xFFFFF26C))
#define VICVectPriority28  (*(REG32 0xFFFFF270))
#define VICVectPriority29  (*(REG32 0xFFFFF274))
#define VICVectPriority30  (*(REG32 0xFFFFF278))
#define VICVectPriority31  (*(REG32 0xFFFFF27C))
                           
#define VIC_VectAdr		(*(REG32 (0xFFFFFF00) ))	// current VectorAdr





/*##############################################################################
## Ethernet Controller
##############################################################################*/

// MAC registers

#define ETH_MAC1		(*(REG32 0xFFE00000))
#define ETH_MAC2		(*(REG32 0xFFE00004))
#define ETH_IPGT		(*(REG32 0xFFE00008))
#define ETH_IPGR		(*(REG32 0xFFE0000C))
#define ETH_CLRT		(*(REG32 0xFFE00010))
#define ETH_MAXF		(*(REG32 0xFFE00014))
#define ETH_PHYSUPP		(*(REG32 0xFFE00018))
#define ETH_TEST		(*(REG32 0xFFE0001C))

// MII management & config registers
#define ETH_MIICFG		(*(REG32 0xFFE00020))
#define ETH_MIICMD		(*(REG32 0xFFE00024))
#define ETH_MIIADR		(*(REG32 0xFFE00028))
#define ETH_MIIWTD		(*(REG32 0xFFE0002C))
#define ETH_MIIRDD		(*(REG32 0xFFE00030))
#define ETH_MIIIND		(*(REG32 0xFFE00034))


#define ETH_SA0			(*(REG32 0xFFE00040))
#define ETH_SA1			(*(REG32 0xFFE00044))
#define ETH_SA2			(*(REG32 0xFFE00048))

// Control Register

#define ETH_COMMAND		(*(REG32 0xFFE00100))
#define ETH_STATUS		(*(REG32 0xFFE00104))

#define ETH_RXDESC		(*(REG32 0xFFE00108))
#define ETH_RXSTAT		(*(REG32 0xFFE0010C))
#define ETH_RXDESCRNO	(*(REG32 0xFFE00110))
#define ETH_RXPRODIX	(*(REG32 0xFFE00114))
#define ETH_RXCONSIX	(*(REG32 0xFFE00118))

#define ETH_TXDESC		(*(REG32 0xFFE0011C))
#define ETH_TXSTAT		(*(REG32 0xFFE00120))
#define ETH_TXDESCRNO	(*(REG32 0xFFE00124))
#define ETH_TXPRODIX	(*(REG32 0xFFE00128))
#define ETH_TXCONSIX	(*(REG32 0xFFE0012C))

#define ETH_TSV0		(*(REG32 0xFFE00158))
#define ETH_TSV1		(*(REG32 0xFFE0015C))
#define ETH_RSV			(*(REG32 0xFFE00160))

#define ETH_FLOWCNTCOUNT (*(REG32 0xFFE00170))
#define ETH_FLOWCNTSTAT	(*(REG32 0xFFE00174))

// Rx Filter registers

#define ETH_RXFILTERCTL			(*(REG32 0xFFE00200))
#define ETH_RXFILTERWOLSTAT		(*(REG32 0xFFE00204))
#define ETH_RXFILTERWOLCLR		(*(REG32 0xFFE00208))

#define ETH_HASHFILTERL			(*(REG32 0xFFE00210))
#define ETH_HASHFILTERH			(*(REG32 0xFFE00214))

// module control registers

#define ETH_INSTSTAT	(*(REG32 0xFFE00FE0))
#define ETH_INTENABLE	(*(REG32 0xFFE00FE4))
#define ETH_INTCLEAR	(*(REG32 0xFFE00FE8))
#define ETH_INTSET		(*(REG32 0xFFE00FEC))

#define ETH_POWERDOWN	(*(REG32 0xFFE00FF4))


                 
/*##############################################################################
## GPIO - General Purpose I/O
##############################################################################*/

#define		GPIO0_Base	0xE0028000
#define		GPIO1_Base	0xE0028010
#define 	GPIO2_Base  0x3FFFC040

/* GPIO Port 0 */
#define GPIO0_IOPIN     (*(REG32 (GPIO0_Base + 0x00))) 
#define GPIO0_IOSET     (*(REG32 (GPIO0_Base + 0x04)))
#define GPIO0_IODIR     (*(REG32 (GPIO0_Base + 0x08)))
#define GPIO0_IOCLR     (*(REG32 (GPIO0_Base + 0x0C)))

/* GPIO Port 1*/
#define GPIO1_IOPIN     (*(REG32 (GPIO1_Base + 0x00))) 
#define GPIO1_IOSET     (*(REG32 (GPIO1_Base + 0x04)))
#define GPIO1_IODIR     (*(REG32 (GPIO1_Base + 0x08)))
#define GPIO1_IOCLR     (*(REG32 (GPIO1_Base + 0x0C)))


/* Fast access Input/Output (GPIO0)  */
#define FGPIO0_IODIR    (*(REG32 (GPIO0_Base + 0x00)))
#define FGPIO0_IOMASK   (*(REG32 (GPIO0_Base + 0x10)))
#define FGPIO0_IOPIN    (*(REG32 (GPIO0_Base + 0x14)))
#define FGPIO0_IOSET    (*(REG32 (GPIO0_Base + 0x18)))
#define FGPIO0_IOCLR    (*(REG32 (GPIO0_Base + 0x1C)))
/* Fast access Input/Output (GPIO1)  */
#define FGPIO1_IODIR    (*(REG32 (GPIO1_Base + 0x00)))
#define FGPIO1_IOMASK   (*(REG32 (GPIO1_Base + 0x10)))
#define FGPIO1_IOPIN    (*(REG32 (GPIO1_Base + 0x14)))
#define FGPIO1_IOSET    (*(REG32 (GPIO1_Base + 0x18)))
#define FGPIO1_IOCLR    (*(REG32 (GPIO1_Base + 0x1C)))
/* Fast access Input/Output (GPIO2)  */
#define FGPIO2_IODIR    (*(REG32 (GPIO2_Base + 0x00)))
#define FGPIO2_IOMASK   (*(REG32 (GPIO2_Base + 0x10)))
#define FGPIO2_IOPIN    (*(REG32 (GPIO2_Base + 0x14)))
#define FGPIO2_IOSET    (*(REG32 (GPIO2_Base + 0x18)))
#define FGPIO2_IOCLR    (*(REG32 (GPIO2_Base + 0x1C)))
/* Fast access Input/Output (GPIO3)  */
#define FGPIO3_IODIR    (*(REG32 (GPIO3_Base + 0x00)))
#define FGPIO3_IOMASK   (*(REG32 (GPIO3_Base + 0x10)))
#define FGPIO3_IOPIN    (*(REG32 (GPIO3_Base + 0x14)))
#define FGPIO3_IOSET    (*(REG32 (GPIO3_Base + 0x18)))
#define FGPIO3_IOCLR    (*(REG32 (GPIO3_Base + 0x1C)))
/* Fast access Input/Output (GPIO4)  */
#define FGPIO4_IODIR    (*(REG32 (GPIO4_Base + 0x00)))
#define FGPIO4_IOMASK   (*(REG32 (GPIO4_Base + 0x10)))
#define FGPIO4_IOPIN    (*(REG32 (GPIO4_Base + 0x14)))
#define FGPIO4_IOSET    (*(REG32 (GPIO4_Base + 0x18)))
#define FGPIO4_IOCLR    (*(REG32 (GPIO4_Base + 0x1C)))


/* Memory Accelerator Module (MAM) */
#define MAMCR          (*((volatile unsigned char *) 0xE01FC000))
#define MAMTIM         (*((volatile unsigned char *) 0xE01FC004))
#define MAMMAP         (*((volatile unsigned char *) 0xE01FC040))

/* Phase Locked Loop (PLL) */
#define PLLCON         (*((volatile unsigned char *) 0xE01FC080))
#define PLLCFG         (*((volatile unsigned char *) 0xE01FC084))
#define PLLSTAT        (*((volatile unsigned short*) 0xE01FC088))
#define PLLFEED        (*((volatile unsigned char *) 0xE01FC08C))

/* VPB Divider */
#define VPBDIV         (*((volatile unsigned char *) 0xE01FC100))


/* External Interrupts */
#define EXTINT         (*((volatile unsigned char *) 0xE01FC140))
#define EXTWAKE        (*((volatile unsigned char *) 0xE01FC144))
#define EXTMODE        (*((volatile unsigned char *) 0xE01FC148))
#define EXTPOLAR       (*((volatile unsigned char *) 0xE01FC14C))

/* Timer 0 */
#define TIMER0_IR      (*((volatile unsigned long *) 0xE0004000))
#define TIMER0_TCR     (*((volatile unsigned long *) 0xE0004004))
#define TIMER0_TC      (*((volatile unsigned long *) 0xE0004008))
#define TIMER0_PR      (*((volatile unsigned long *) 0xE000400C))
#define TIMER0_PC      (*((volatile unsigned long *) 0xE0004010))
#define TIMER0_MCR     (*((volatile unsigned long *) 0xE0004014))
#define TIMER0_MR0     (*((volatile unsigned long *) 0xE0004018))
#define TIMER0_MR1     (*((volatile unsigned long *) 0xE000401C))
#define TIMER0_MR2     (*((volatile unsigned long *) 0xE0004020))
#define TIMER0_MR3     (*((volatile unsigned long *) 0xE0004024))
#define TIMER0_CCR     (*((volatile unsigned long *) 0xE0004028))
#define TIMER0_CR0     (*((volatile unsigned long *) 0xE000402C))
#define TIMER0_CR1     (*((volatile unsigned long *) 0xE0004030))
#define TIMER0_CR2     (*((volatile unsigned long *) 0xE0004034))
#define TIMER0_CR3     (*((volatile unsigned long *) 0xE0004038))
#define TIMER0_EMR     (*((volatile unsigned long *) 0xE000403C))

/* Timer 1 */
#define TIMER1_IR      (*((volatile unsigned long *) 0xE0008000))
#define TIMER1_TCR     (*((volatile unsigned long *) 0xE0008004))
#define TIMER1_TC      (*((volatile unsigned long *) 0xE0008008))
#define TIMER1_PR      (*((volatile unsigned long *) 0xE000800C))
#define TIMER1_PC      (*((volatile unsigned long *) 0xE0008010))
#define TIMER1_MCR     (*((volatile unsigned long *) 0xE0008014))
#define TIMER1_MR0     (*((volatile unsigned long *) 0xE0008018))
#define TIMER1_MR1     (*((volatile unsigned long *) 0xE000801C))
#define TIMER1_MR2     (*((volatile unsigned long *) 0xE0008020))
#define TIMER1_MR3     (*((volatile unsigned long *) 0xE0008024))
#define TIMER1_CCR     (*((volatile unsigned long *) 0xE0008028))
#define TIMER1_CR0     (*((volatile unsigned long *) 0xE000802C))
#define TIMER1_CR1     (*((volatile unsigned long *) 0xE0008030))
#define TIMER1_CR2     (*((volatile unsigned long *) 0xE0008034))
#define TIMER1_CR3     (*((volatile unsigned long *) 0xE0008038))
#define TIMER1_EMR     (*((volatile unsigned long *) 0xE000803C))

/* Pulse Width Modulator (PWM) */
#define PWM_IR         (*((volatile unsigned long *) 0xE0014000))
#define PWM_TCR        (*((volatile unsigned long *) 0xE0014004))
#define PWM_TC         (*((volatile unsigned long *) 0xE0014008))
#define PWM_PR         (*((volatile unsigned long *) 0xE001400C))
#define PWM_PC         (*((volatile unsigned long *) 0xE0014010))
#define PWM_MCR        (*((volatile unsigned long *) 0xE0014014))
#define PWM_MR0        (*((volatile unsigned long *) 0xE0014018))
#define PWM_MR1        (*((volatile unsigned long *) 0xE001401C))
#define PWM_MR2        (*((volatile unsigned long *) 0xE0014020))
#define PWM_MR3        (*((volatile unsigned long *) 0xE0014024))
#define PWM_MR4        (*((volatile unsigned long *) 0xE0014040))
#define PWM_MR5        (*((volatile unsigned long *) 0xE0014044))
#define PWM_MR6        (*((volatile unsigned long *) 0xE0014048))
#define PWM_CCR        (*((volatile unsigned long *) 0xE0014028))
#define PWM_CR0        (*((volatile unsigned long *) 0xE001402C))
#define PWM_CR1        (*((volatile unsigned long *) 0xE0014030))
#define PWM_CR2        (*((volatile unsigned long *) 0xE0014034))
#define PWM_CR3        (*((volatile unsigned long *) 0xE0014038))
#define PWM_EMR        (*((volatile unsigned long *) 0xE001403C))
#define PWM_PCR        (*((volatile unsigned long *) 0xE001404C))
#define PWM_LER        (*((volatile unsigned long *) 0xE0014050))

/* Universal Asynchronous Receiver Transmitter 0 (UART0) */
#define UART0_RBR      (*((volatile unsigned char *) 0xE000C000))
#define UART0_THR      (*((volatile unsigned char *) 0xE000C000))
#define UART0_IER      (*((volatile unsigned char *) 0xE000C004))
#define UART0_IIR      (*((volatile unsigned char *) 0xE000C008))
#define UART0_FCR      (*((volatile unsigned char *) 0xE000C008))
#define UART0_LCR      (*((volatile unsigned char *) 0xE000C00C))
#define UART0_MCR      (*((volatile unsigned char *) 0xE000C010))
#define UART0_LSR      (*((volatile unsigned char *) 0xE000C014))
#define UART0_MSR      (*((volatile unsigned char *) 0xE000C018))
#define UART0_SCR      (*((volatile unsigned char *) 0xE000C01C))
#define UART0_DLL      (*((volatile unsigned char *) 0xE000C000))
#define UART0_DLM      (*((volatile unsigned char *) 0xE000C004))

/* Universal Asynchronous Receiver Transmitter 1 (UART1) */
#define UART1_RBR      (*((volatile unsigned char *) 0xE0010000))
#define UART1_THR      (*((volatile unsigned char *) 0xE0010000))
#define UART1_IER      (*((volatile unsigned char *) 0xE0010004))
#define UART1_IIR      (*((volatile unsigned char *) 0xE0010008))
#define UART1_FCR      (*((volatile unsigned char *) 0xE0010008))
#define UART1_LCR      (*((volatile unsigned char *) 0xE001000C))
#define UART1_MCR      (*((volatile unsigned char *) 0xE0010010))
#define UART1_LSR      (*((volatile unsigned char *) 0xE0010014))
#define UART1_MSR      (*((volatile unsigned char *) 0xE0010018))
#define UART1_SCR      (*((volatile unsigned char *) 0xE001001C))
#define UART1_DLL      (*((volatile unsigned char *) 0xE0010000))
#define UART1_DLM      (*((volatile unsigned char *) 0xE0010004))

/* I2C Interface */
#define I2C_I2CONSET   (*((volatile unsigned char *) 0xE001C000))
#define I2C_I2STAT     (*((volatile unsigned char *) 0xE001C004))
#define I2C_I2DAT      (*((volatile unsigned char *) 0xE001C008))
#define I2C_I2ADR      (*((volatile unsigned char *) 0xE001C00C))
#define I2C_I2SCLH     (*((volatile unsigned short*) 0xE001C010))
#define I2C_I2SCLL     (*((volatile unsigned short*) 0xE001C014))
#define I2C_I2CONCLR   (*((volatile unsigned char *) 0xE001C018))

/* SPI0 (Serial Peripheral Interface 0) */
#define SPI0_SPCR      (*((volatile unsigned char *) 0xE0020000))
#define SPI0_SPSR      (*((volatile unsigned char *) 0xE0020004))
#define SPI0_SPDR      (*((volatile unsigned char *) 0xE0020008))
#define SPI0_SPCCR     (*((volatile unsigned char *) 0xE002000C))
#define SPI0_SPTCR     (*((volatile unsigned char *) 0xE0020010))
#define SPI0_SPTSR     (*((volatile unsigned char *) 0xE0020014))
#define SPI0_SPTOR     (*((volatile unsigned char *) 0xE0020018))
#define SPI0_SPINT     (*((volatile unsigned char *) 0xE002001C))

/* SPI1 (Serial Peripheral Interface 1) */
#define SPI1_SPCR      (*((volatile unsigned char *) 0xE0030000))
#define SPI1_SPSR      (*((volatile unsigned char *) 0xE0030004))
#define SPI1_SPDR      (*((volatile unsigned char *) 0xE0030008))
#define SPI1_SPCCR     (*((volatile unsigned char *) 0xE003000C))
#define SPI1_SPTCR     (*((volatile unsigned char *) 0xE0030010))
#define SPI1_SPTSR     (*((volatile unsigned char *) 0xE0030014))
#define SPI1_SPTOR     (*((volatile unsigned char *) 0xE0030018))
#define SPI1_SPINT     (*((volatile unsigned char *) 0xE003001C))

/* Real Time Clock */
#define RTC_ILR        (*((volatile unsigned char *) 0xE0024000))
#define RTC_CTC        (*((volatile unsigned short*) 0xE0024004))
#define RTC_CCR        (*((volatile unsigned char *) 0xE0024008))
#define RTC_CIIR       (*((volatile unsigned char *) 0xE002400C))
#define RTC_AMR        (*((volatile unsigned char *) 0xE0024010))
#define RTC_CTIME0     (*((volatile unsigned long *) 0xE0024014))
#define RTC_CTIME1     (*((volatile unsigned long *) 0xE0024018))
#define RTC_CTIME2     (*((volatile unsigned long *) 0xE002401C))
#define RTC_SEC        (*((volatile unsigned char *) 0xE0024020))
#define RTC_MIN        (*((volatile unsigned char *) 0xE0024024))
#define RTC_HOUR       (*((volatile unsigned char *) 0xE0024028))
#define RTC_DOM        (*((volatile unsigned char *) 0xE002402C))
#define RTC_DOW        (*((volatile unsigned char *) 0xE0024030))
#define RTC_DOY        (*((volatile unsigned short*) 0xE0024034))
#define RTC_MONTH      (*((volatile unsigned char *) 0xE0024038))
#define RTC_YEAR       (*((volatile unsigned short*) 0xE002403C))
#define RTC_ALSEC      (*((volatile unsigned char *) 0xE0024060))
#define RTC_ALMIN      (*((volatile unsigned char *) 0xE0024064))
#define RTC_ALHOUR     (*((volatile unsigned char *) 0xE0024068))
#define RTC_ALDOM      (*((volatile unsigned char *) 0xE002406C))
#define RTC_ALDOW      (*((volatile unsigned char *) 0xE0024070))
#define RTC_ALDOY      (*((volatile unsigned short*) 0xE0024074))
#define RTC_ALMON      (*((volatile unsigned char *) 0xE0024078))
#define RTC_ALYEAR     (*((volatile unsigned short*) 0xE002407C))
#define RTC_PREINT     (*((volatile unsigned short*) 0xE0024080))
#define RTC_PREFRAC    (*((volatile unsigned short*) 0xE0024084))

/* A/D Converter */
#define ADCR           (*((volatile unsigned long *) 0xE0034000))
#define ADDR           (*((volatile unsigned long *) 0xE0034004))

/* Watchdog */
#define WDMOD          (*((volatile unsigned char *) 0xE0000000))
#define WDTC           (*((volatile unsigned long *) 0xE0000004))
#define WDFEED         (*((volatile unsigned char *) 0xE0000008))
#define WDTV           (*((volatile unsigned long *) 0xE000000C))



#endif  // __LPC21xx_H
